Desktop computer systems typically use a graphics controller to display 3D images on a monitor. The graphics controller receives instructions regarding what to draw by driver software running on a processor. The processor and the graphics controller are typically coupled together by a system logic device (often referred to as a “chipset”). For systems that are being used for computer-aided design or for 3D games, the command traffic between the processor and the graphics controller can be considerable. The communication paths between the processor and the graphics controller can often sustain substantially more command bandwidth than if the command traffic is routed through memory, since the memory system must sustain twice the bandwidth in order to transfer the same commands. This is because the commands must be written from the processor into memory and later read back from memory by the graphics controller.
One solution to the limited memory bandwidth problem would be to write command data directly from the processor to the graphics device, eliminating the writes and reads to and from system memory. However, when command data is written directly by the processor to the graphics controller, processor cycles can be lost if the aggregate buffering capacity of the graphics controller and system logic device is consumed. When this happens, the processor is forced to wait for buffer space to clear before it can proceed. Because the graphics driver may need to perform complex calculations and these calculations can be forced to wait for simple command write operations, a substantial waste of processing power is experienced.
If the amount of buffer space in the system logic device were increased, the processor would experience less waiting for buffer space to clear. The system logic device could include a substantial cache that may be used to buffer enough command data so that the commands may be read by the graphics controller directly from the system logic device. However, because the system logic device has no way of knowing whether the data written to the buffers will ever be needed again by the graphics controller or by some other system agent, this solution has the problem of requiring that all of the data written to the buffers also be written out to system memory, thereby negatively impacting overall computer system performance.